Semiconductor device and semiconductor device manufacturing method

ABSTRACT

The present invention aims to improve the accuracy and stability when removing an insulating film at a bottom of a TSV to allow a through hole to open toward a connection target electrode. A semiconductor device manufacturing method including: forming a through hole in a semiconductor substrate by using anisotropic etching performed from a first surface side of the semiconductor substrate; forming a thin film being an insulating film on an entire inner surface of the through hole; forming a carbon-containing thin film using plasma deposition on the first surface including an opening edge portion of the through hole; engraving an inner bottom of the through hole by using anisotropic plasma etching with the carbon-containing thin film as a mask; removing the carbon-containing thin film by ashing; and forming a through-substrate electrode in the through hole.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.16/308,071, filed on Dec. 7, 2018, which is a national stage applicationunder 35 U.S.C. 371 and claims the benefit of PCT Application No.PCT/JP2017/017327 having an international filing date of May 8, 2017,which designated the United States, which PCT application claimed thebenefit of Japanese Patent Application No. 2016-118730 filed Jun. 15,2016, the entire disclosures of each of which are incorporated herein byreference.

TECHNICAL FIELD

The present technology relates to a semiconductor device and asemiconductor device manufacturing method.

BACKGROUND ART

In recent years, the development of three-dimensional mountingtechnology using a through silicon via (TSV) is gaining momentum as amethod to realize further enhanced functionality of semiconductordevices. Although the size of the current TSV has a width of several μmand an aspect ratio of about 10 or less, it is expected to achievefurther downsized TSV with higher integration in order to achieve moresignal transmission volume and smaller device size.

The formation of TSV is implemented by first forming a through holepenetrating a silicon substrate to reach a connection target electrodeor its vicinity, forming an insulating film on a field portion and aninner surface of the through hole, removing the insulating film at thebottom of the through hole to allow the through hole to open toward theconnection target electrode, and burying a barrier metal film and ametal inside the through hole to form a through-substrate electrode.

Here, Patent Documents 1 and 2 disclose technologies of removing theinsulating film at the bottom of the TSV to allow the through hole toopen toward the connection target electrode.

Patent Document 1 discloses that an insulating film provided on a fieldportion and an inner surface of a through hole is formed by using aninsulating film with low coverage so that the insulating film on theinner surface near an upper portion of the through hole becomes thickerso as to form the through hole in an overhanging shape. This makes itpossible to remove the insulating film alone at the bottom of thethrough hole while protecting the insulating film on the inner surfaceof the through hole.

In Patent Document 2, an insulating film provided on a field portion andan inner surface of a through hole is formed by using an insulating filmwith high coverage, and a resist film is formed above the field portionand the inner surface of the through hole from above the insulating filmby a lithography method so that the width in the vicinity of the upperportion of the through hole becomes narrower than the width of thebottom of the through hole. This makes it possible to remove theinsulating film alone at the bottom of the through hole while protectingthe insulating film on the inner surface of the through hole.

CITATION LIST Patent Document

Patent Document 1: Japanese Patent Application Laid-Open No. 2014-110287

Patent Document 2: Japanese Patent Application Laid-Open No. 2010-114201

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

The technique described in Patent Document 1 described above forms theinsulating film inside the through hole so as to have an overhangingshape, leading to reduction of the opening width of the upper portion ofthe through hole due to compression by the insulating film. In enhancingthe miniaturization of TSV compared to the current status, the reductionof the opening width of the through hole would have a greater influenceon the processing difficulty degree. Especially when the aspect ratio ofthe through hole is 10 or more, the influence on the processingdifficulty degree becomes extremely large. In addition, since the shapeof the through hole is inversely tapered, it has also a great influenceon the difficulty degree in burying the metal. On the other hand, in acase where the deposition amount of the insulating film with lowcoverage is reduced in order to avoid such influence, the upperinsulating film might vanish before opening the bottom insulating film,causing the etching to reach the silicon substrate.

Furthermore, in the technology described in Patent Document 2 describedabove, enhancing the miniaturization of the TSV as compared with thecurrent status might make the influence of the misalignment occurring atthe time of mask alignment at the time of lithography noticeable, makingit difficult to stably expose to the bottom of the hole, causing aprocessing accuracy problem.

The present technology has been made in view of the above problems andaims to improve the accuracy and stability when removing the insulatingfilm at the bottom of the TSV to allow the through hole to open towardthe connection target electrode.

Solutions to Problems

One aspect of the present technology is a semiconductor devicemanufacturing method including: a first step of forming a through holein a semiconductor substrate by using anisotropic etching performed froma first surface side of the semiconductor substrate; a second step offorming a thin film being an insulating film on an entire inner surfaceof the through hole; a third step of forming a carbon-containing thinfilm using plasma deposition on the first surface including an openingedge portion of the through hole; a fourth step of engraving an innerbottom of the through hole by using anisotropic plasma etching with thecarbon-containing thin film as a mask; a fifth step of removing thecarbon-containing thin film by ashing, and a sixth step of forming athrough-substrate electrode in the through hole.

Another aspect of the present technology is a semiconductor deviceincluding: a semiconductor substrate; a wiring layer formed to bestacked on a first surface of the semiconductor substrate; a metal filmconstituting a portion of the wiring layer; a first insulating filmconstituting a portion of the wiring layer and provided adjacent to thesemiconductor substrate side of the metal film; a through-substrateelectrode penetrating from the first surface of the semiconductorsubstrate and from a second surface of the semiconductor substrateopposite to the first surface, to the metal film; a second insulatingfilm interposed between the through-substrate electrode and thesemiconductor substrate; and a third insulating film formed to adhere toa second surface-side end portion of the second insulating film.

Note that the semiconductor device described above includes variousaspects such as being implemented in a state of being incorporated inanother device or being implemented together with other methods.Furthermore, the present technology can also be realized as a systemincluding the semiconductor device. In addition, the above-describedmethod of manufacturing a semiconductor device includes various aspectssuch as being implemented as a part of another manufacturing method.

Effects of the Invention

According to the present technology, it is possible to improve theaccuracy and stability when removing the insulating film at the bottomof the TSV to allow the through hole to open toward the connectiontarget electrode. Note that effects described in the present descriptionare provided for purposes of exemplary illustration and are not intendedto be limiting. Still other additional effects may also be contemplated.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram schematically illustrating a cross section of a mainportion of a semiconductor device according to a first embodiment.

FIG. 2A is a diagram schematically illustrating a method ofmanufacturing a main portion of a semiconductor device according to afirst embodiment.

FIG. 2B is a diagram schematically illustrating a method ofmanufacturing a main portion of a semiconductor device according to thefirst embodiment.

FIG. 3A is a diagram schematically illustrating a method formanufacturing a main portion of the semiconductor device according tothe first embodiment.

FIG. 3B is a diagram schematically illustrating a method formanufacturing a main portion of the semiconductor device according tothe first embodiment.

FIG. 4A is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according to afirst embodiment.

FIG. 4B is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe first embodiment.

FIG. 5A is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe first embodiment.

FIG. 5B is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe first embodiment.

FIG. 6A is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe first embodiment.

FIG. 6B is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe first embodiment.

FIG. 7A is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe first embodiment.

FIG. 7B is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe first embodiment.

FIG. 8A is a diagram illustrating a shape of an additional insulatingfilm.

FIG. 8B is a diagram illustrating a shape of an additional insulatingfilm.

FIG. 9A is a diagram illustrating a shape of an additional insulatingfilm.

FIG. 9B is a diagram illustrating a shape of an additional insulatingfilm.

FIG. 10A is a diagram schematically illustrating a method ofmanufacturing a main portion of a semiconductor device according to asecond embodiment.

FIG. 10B is a diagram schematically illustrating a method ofmanufacturing a main portion of a semiconductor device according to thesecond embodiment.

FIG. 11A is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe second embodiment.

FIG. 11B is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe second embodiment.

FIG. 12A is a diagram schematically illustrating a method ofmanufacturing a main portion of a semiconductor device according to athird embodiment.

FIG. 12B is a diagram schematically illustrating a method ofmanufacturing a main portion of a semiconductor device according to thethird embodiment.

FIG. 13A is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe third embodiment.

FIG. 13B is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe third embodiment.

FIG. 14 is a diagram schematically illustrating a method ofmanufacturing a main portion of a semiconductor device according to afourth embodiment.

FIG. 15 is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe fourth embodiment.

FIG. 16 is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe fourth embodiment.

FIG. 17 is a diagram schematically illustrating a method formanufacturing a main portion of a semiconductor device according to afifth embodiment.

FIG. 18 is a diagram schematically illustrating a method formanufacturing a main portion of the semiconductor device according tothe fifth embodiment.

FIG. 19 is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe fifth embodiment.

FIG. 20 is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe fifth embodiment.

FIG. 21 is a diagram schematically illustrating a method ofmanufacturing a main portion of a semiconductor device according to asixth embodiment.

FIG. 22 is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe sixth embodiment.

FIG. 23 is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe sixth embodiment.

FIG. 24 is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe sixth embodiment.

FIG. 25 is a diagram schematically illustrating a method ofmanufacturing a main portion of the semiconductor device according tothe sixth embodiment.

FIG. 26A is a diagram illustrating a difference between first engravingand second engraving.

FIG. 26B is a diagram illustrating a difference between the firstengraving and the second engraving.

FIG. 27A is a diagram illustrating a difference between the firstengraving and the second engraving.

FIG. 27B is a diagram illustrating a difference between the firstengraving and the second engraving.

FIG. 28A is a diagram illustrating a difference between the firstengraving and the second engraving.

FIG. 28B is a diagram illustrating a difference between the firstengraving and the second engraving.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present technology will be described in the followingorder.

(A) First embodiment:

(B) Second Embodiment:

(C) Third embodiment:

(D) Fourth Embodiment:

(E) Fifth embodiment:

(F) Sixth Embodiment:

(A) First Embodiment

FIG. 1 is a diagram schematically illustrating a cross section of a mainportion of a semiconductor device 100 according to the presentembodiment.

The semiconductor device 100 has a configuration in which a wiring layer20 including an insulating film, a metal film, a transistor element, orthe like, is provided on a semiconductor substrate 10 such as a siliconsubstrate. FIG. 1 illustrates a state in which the wiring layer 20 isstacked on the semiconductor substrate 10 and thereafter the substrateis reversed, having the wiring layer 20 positioned below thesemiconductor substrate 10. The thickness of the semiconductor substrate10 is 1 μm to 10 μm, for example.

Note that in the following description of the surface of thesemiconductor substrate 10, the surface on the lower side in FIG. 1(side on which the wiring layer 20 is stacked) will be denoted as afront surface 10 a, and the surface on the upper side in FIG. 1 as aback surface 10 b in some cases.

Furthermore, a side on the wiring layer 20 closer to the semiconductorsubstrate 10 will be referred to as a lower side, and a side away fromthe semiconductor substrate 10 as an upper side.

The wiring layer 20 includes at least an insulating film 21 as a firstinsulating film and a metal film 22 (in FIG. 1, the insulating film 21and the metal film 22 alone are illustrated), with the insulating film21 being formed adjacent to a lower layer side of the metal film 22. Themetal film 22 constitutes an electrode in the wiring layer 20.

A through hole 11 is formed in the semiconductor substrate 10. Thethrough hole 11 has a form penetrating from the back surface 10 b as afirst surface of the semiconductor substrate 10 to the front surface 10a as a second surface on the opposite side thereof and furtherpenetrating a layer below the metal film 22 in the wiring layer 20 toreach the metal film 22. The through hole 11 may partially include ahole formed in the metal film 22, and for example, may include a recessformed by etching or the like on the metal film 22 exposed at the bottomof the through hole 11.

On the semiconductor substrate 10, an insulating film 30 is continuouslyformed over the entire surface along the inner surface of the throughhole 11 and the surface along the back surface 10 b (at least in thevicinity of opening periphery of the through hole 11 of the back surface10 b) of the semiconductor substrate 10. The insulating film 30 isformed so as to cover the inner surface of the through hole 11 and theback surface 10 b of the semiconductor substrate 10 with a substantiallyconstant thickness and is interposed between a through-substrateelectrode 12 formed in the through hole 11, and the semiconductorsubstrate 10. However, the insulating film 21 and the metal film 22constituting the side surface and the bottom surface at the bottom ofthe through hole 11 of the semiconductor device 100 are not covered withthe insulating film 30. The insulating film 30 is formed by using a lowdielectric constant interlayer insulating film material (low-kmaterial), and is formed by using, for example, at least one of SiO₂,SiN, SiON, SiOC, or SiOCH.

The through hole 11 has a size inside the insulating film 30, being 50nm to 500 nm in an opening width a, and an aspect ratio (=b/a (b is thedepth of the through hole 11)) of 10 or more. Since the through hole 11is formed through the semiconductor substrate 10, the depth b of thethrough hole 11 is greater than the thickness of the semiconductorsubstrate 10, for example, the depth b is about 1 μm.

At least a portion of the vicinity of the opening of the through hole 11of the insulating film 30 is constituted with an additional insulatingfilm 32 as a third insulating film formed by a process different fromthe process for an insulating film main body 31 as a second insulatingfilm constituting substantially the whole of the insulating film 30. Inthe insulating film 30 illustrated in FIG. 1, the additional insulatingfilm 32 stacked on the insulating film main body 31 forms a corner ofthe opening of the through hole 11. The additional insulating film 32may be formed not merely on the corner of the opening of the throughhole 11 but also on the insulating film main body 31. The additionalinsulating film 32 is formed by using at least one of SiO₂, SiON, SiN,SiOC, or SiOCH.

In the insulating film 30, with the presence of the additionalinsulating film 32, it is possible to improve uniformity of thethickness of the insulating film 30 and the flatness of the frontsurface (side not facing the semiconductor substrate 10) as comparedwith the case of forming the insulating film 30 with the insulating filmmain body 31 alone.

The through-substrate electrode 12 (TSV) is buried inside the insulatingfilm 30 formed along the inner surface of the through hole 11. Thethrough-substrate electrode 12 includes a barrier metal film and ametal. The barrier metal film is formed by using at least one of Ti,TiN, Ta, or TaN. The metal is formed by using at least one of Cu, W, orAl.

The barrier metal film is a barrier film for preventing diffusion ofmetal and is continuously formed over an entire surface along the innerside of the insulating film 30 formed along the inner surface of thethrough hole 11 and the entire surface along the back surface 10 b inthe vicinity of the opening of the through hole 11. That is, a barriermetal film is formed to be interposed between the semiconductorsubstrate 10 and the metal.

FIGS. 2A-7B are diagrams schematically illustrating a method ofmanufacturing a main portion of the semiconductor device 100 describedabove.

The manufacturing method illustrated in these figures can be applied tomanufacturing methods such as “Via Last TSV” and “Via after bondig”, forexample. “Via Last TSV” is a manufacturing method of first forming thewiring layer 20 on the semiconductor substrate 10 and thereafter forminga TSV to reach the wiring layer 20 from the back surface 10 b side ofthe semiconductor substrate 10. The “Via after bondig” is amanufacturing method of first laminating and integrating two or moresemiconductor substrates each having undergone wafer processing stepssuch as stacking of wiring layers, and then forming TSV to penetrate adepth of one semiconductor substrate or more from either the front orback side of the integrated substrate so as to reach anothersemiconductor substrate.

First, the semiconductor substrate 10 on which the wiring layer 20 isstacked on the front surface 10 a side of the semiconductor substrate 10is prepared, and then, the semiconductor substrate 10 is mounted withits back surface 10 b facing upwards, on a wafer stage of asemiconductor exposure apparatus for lithography (FIG. 2A).

Next, a resist 40 is formed on the back surface 10 b of thesemiconductor substrate 10 by using a photolithography technology FIG.2B. The resist 40 has an opening 41 formed at a position where thethrough hole 11 is to be formed.

Next, anisotropic plasma etching is performed on the resist 40 to form athrough hole 11A (FIG. 3A). The through hole 11A formed in this step hasa depth to reach the insulating film 21 from the back surface 10 b ofthe semiconductor substrate 10, penetrating through the semiconductorsubstrate 10. Note that in this step, the insulating film 21 may bepartially engraved by etching, and in this case, the through hole 11A isformed to a depth to reach a midway depth of the insulating film 21.

Next, ashing is performed to remove the resist to form a high coverageinsulating film 30A (not illustrated) over the entire surface along theinner surface (including the bottom surface) of the through hole 11A andalong the back surface 10 b of the semiconductor substrate 10 (at leastvicinity of the opening of the through hole 11 of the back surface 10 b)(FIG. 3B). The insulating film 30A is formed to cover the through hole11 and the back surface 10 b of the semiconductor substrate 10, with asubstantially constant thickness. The insulating film 30A is formed byusing at least one of SiO₂, SiN, or SiON.

The insulating film 30A is formed by an atomic layer deposition (ALD)method, for example. Furthermore, the insulating film 30A can be formedby a thermal oxidation method, a low pressure chemical vapor deposition(LP-CVD) method, and a plasma-enhanced chemical vapor deposition(PE-CVD) method, for example.

The insulating film 30A formed by an ALD method is performed so as toform a film with high coverage by using an aminosilane-based precursorgas. The insulating film 30A formed by the LP-CVD method is formed byusing SiH₄ or tetraethoxysilane (TEOS) as a precursor gas for SiO₂. Inthe case of SiN, SiH₄ or dichlorosilane (DCS) is used as a precursorgas. Note that formation of the insulating film 30A needs to be donebefore formation of the wiring layer 20 in a case where the LP-CVDmethod is used, since the LP-CVD method is high-temperature processing.In the formation of the insulating film 30A using the PE-CVD method, itis preferable to use organic silane as a precursor gas rather than SiH₄.In the case of SiO₂, it is possible to use TEOS, methylsilane (1MS),dimethylsilane (2MS), trimethylsilane (3MS), tetramethylsilane (4MS), orthe like, as the precursor gas. In the case of SiN, Trisilylamine (TSA)can be used as the precursor gas. As a plasma source, PE-CVD byradial-line-slot antenna (RLSA) system has been reported as a highcoverage method (Reference: Jpn. J. Appl. Phys. 48 (2009) 126001). SiOCand SiOCH are formed by the ALD method or the PE-CVD method. In thiscase, as the precursor gas, it is possible to useBistrimethylsilylmethane (BTMSM), methyltrimethoxysilane (MTMS),tetramethylcyclotelrasiloxane (TMCTS), octamethylcyclotetrasiloxane(OMCTS), and Decamethylcyclopentasiloxane (DMCPS) in addition to theabove 1MS, 2MS, 3MS, and 4MS. Note that in a case where the insulatingfilm 30A is formed as a process after forming the wiring layer 20 as inthe present embodiment, the insulating film 30A is formed in processingperformed at a low temperature of less than 400° C.

Next, the bottom of the through hole 11A is engraved by etching toachieve a depth at which the metal film 22 is exposed at the bottom ofthe through hole 11A (FIGS. 4A to 5A and FIGS. 5B to 6B). As describedbelow, the manufacturing method according to the present embodiment usesa technique of suppressing occurrence of a damage to the insulating film30A other than the bottom of the through hole 11A by this etching.

First, a carbon-containing thin film 50 for protecting the insulatingfilm 30A formed on the back surface 10 b of the semiconductor substrate10 is formed (FIG. 4A). It is possible to form the carbon-containingthin film 50 by using plasma having at least one of fluorocarbons CF₄,C₄F₈, C₄F₆, etc.) or hydrofluorocarbons (CHF₃, CH₂F₂, CH₃F, C₅HF₇, etc.)as the process gas in a low ion energy state (for example, substratebias of 100V or less).

The carbon-containing thin film 50 is formed as a thin film with lowcoverage. Therefore, as illustrated in FIG. 4A, while thecarbon-containing thin film 50 adheres to the back surface 10 b side ofthe semiconductor substrate 10 with a constant thickness or more, theformation of the film onto the inner surface of the through hole 11A isin such a degree that the film thickness gradually decreases toward thedeeper portion of the through hole 11A in the vicinity of the opening ofthe through hole 11A (in the range of about several nm to several tensnm from the opening). The carbon-containing thin film 50 is formed witha thickness d of, for example, about 10 nm to 100 nm on the back surface10 b side of the semiconductor substrate 10.

The carbon-containing thin film 50 is formed in a shape protrudingtoward the center of the through hole 11A in the vicinity of the openingof the through hole 11A, and the film thickness gradually decreasestoward the deeper portion of the through hole 11A as described above,leading to an overhanging shape of the carbon-containing thin film 50 inthe vicinity of the opening of the through hole 11A. A protrusion amountx toward the center of the through hole 11A of the carbon-containingthin film 50 is about 3 nm in a case where the thickness d of thecarbon-containing thin film 50 is about 10 nm to 100 nm. Therefore, whenthe through hole 11A has an opening width of about 50 nm on the innerside of the insulating film 30A, an opening width in a state where thecarbon-containing thin film 50 has been formed would be about 43 nm.

Next, the bottom of the through hole 11A is engraved by anisotropicplasma etching using the carbon-containing thin film 50 as a mask (FIG.4B). This anisotropic plasma etching uses plasma having at least one offluorocarbons (CF4, C4F8, C4F6, etc.) or hydrofluorocarbons (CHF3,CH2F2, CH3F, C5HF7, etc.) as the process gas in a high ion energy state(for example, substrate bias of 500V or more). Note that the process gasmay contain at least one of hydrocarbon (CH4, C2H4, etc.), He, Ar, O2,CO, or N2. At this time, the ratio of C in the gas chemistry isdecreased compared with the case of forming the carbon-containing thinfilm 50 to prevent clogging of the opening of the through hole 11A dueto excess polymer. Execution time for the anisotropic etching is set toa time that the carbon-containing thin film 50 formed on the backsurface 10 b of the semiconductor substrate 10 would not vanish due tothe etching.

Next, the carbon-containing thin film 50 is removed by ashing (FIG. 5A).This ashing is performed by plasma discharge including, for example, O2,H2, or N2 to remove the carbon-containing thin film 50 and remove Cpolymer adhered during the anisotropic plasma etching. The processingtime may be set to a time period sufficient to remove the C polymeradhering to the inside of the carbon-containing thin film 50 and thethrough hole 11A.

Thereafter, processing of plasma deposition of the carbon-containingthin film 50 similar to FIGS. 4A to 5A, plasma etching using thecarbon-containing thin film 50 as a mask, ashing of removing thecarbon-containing thin film 50 and the C polymer adhered during etching(FIG. 5B to FIG. 6B) is repeatedly performed in a short cycle. In thismanner, by repeating the plasma deposition, the plasma etching, and theashing in a short cycle, it is possible to gradually engrave the bottomof the through hole 11A. This repetitive processing is performed untilthe bottom of the through hole 11A reaches the metal film 22 to form thethrough hole 11.

As described above, according to the present embodiment, the processingof the plasma deposition, the plasma etching, and the ashing is repeatedin a short cycle to engrave the bottom of the through hole 11A to formthe through hole 11. This makes it possible to eliminate the necessityof using a lithography technology and possible to complete processingwithin a same plasma apparatus.

Furthermore, since it is possible to reduce the thickness of thecarbon-containing thin film 50 formed by each of plasma depositionprocessing, enabling decreasing the oppression of opening width of thethrough hole 11A by the carbon-containing thin film 50, leading tostabilized processing of the bottom of the through hole 11A.Furthermore, the carbon-containing thin film 50 can be easily removed,making it possible to minimize the influence on the subsequent process.

Note that there is no need to match processing times of plasmadeposition, plasma etching, and ashing in each of cycles, and theprocessing time may be adjusted at each of cycles to adjust the filmthickness and degree of coverage. Furthermore, it is allowable toperform a washing step of removing the processing residues deposited onthe bottom of the through hole 11A during or after the repetitiveprocessing described above.

Furthermore, there is a possibility that a damage occurring in theabove-described repetitive processing causes reduction of the thicknessof the insulating film 30 formed on the back surface 10 b of thesemiconductor substrate 10 (FIGS. 6B and 8A), scraping of the openingcorner of the through hole 11A of the insulating film 30 formed on theback surface 10 b of the semiconductor substrate 10 (FIGS. 6A and 8B),or roughening of the surface (FIG. 9A) of the insulating film 30 formedon the back surface 10 b of the semiconductor substrate 10. In thesecases, as illustrated in FIGS. 7A, 8A, 6A, 8B, and 9A, the low coverageadditional insulating film 32 may be formed on the insulating film 30Aas the insulating film main body 31 so as to compensate for roughness,decrease in film thickness, and rounding of the corner.

For example, SiO₂, SiN, or SiON may be used as the additional insulatingfilm 32, and the film can be formed by a PE-CVD method using SiH₄,Si₂H₆, Si₃H₈, or TEOS as a precursor gas and using CCP or ICP plasma asa plasma source, for example. In the case of SiOC or SiOCH, theprecursor gas same as that for the insulating film 30 can be used. Theadditional insulating film 32 is to be formed with a thickness (forexample, about 10 nm to 100 nm) to such an extent that the amount offilm formed on the bottom of the through hole 11 is extremely small.Alternatively, the additional insulating film 32 may be SiON or SiN.

Furthermore, the surface of the additional insulating film 32 may beflattened with chemical mechanical polishing (CMP) or the like toeliminate irregularities on the surface or uniformize the thickness ofthe insulating film 30.

In addition, as illustrated in FIG. 9B, there is a possibility that thedamage occurring in the above-described repetitive processing causesformation of wave-like irregularities in a direction along a depthdirection on the inner surface of the through hole 11A engraved byrepetition of plasma deposition, plasma etching, and ashing, in a shortcycle. In a case where the wave-like irregularities are left, a shapeobtained by front/back inverting the wave-like irregularities is goingto be formed in the structure of the bottom of the through-substrateelectrode 12.

Thereafter, a barrier metal film and a metal are buried in the throughhole 11 (FIG. 7B). The barrier metal film is formed by using Ti, TiN,Ta, or TaN by a sputtering method, the ALD method, or the like. Themetal is formed by using Cu, W, or Al, for example, by an electrolyticplating method.

Main portions of the semiconductor device 100 according to the presentembodiment can be produced by using the manufacturing method describedabove.

(B) Second Embodiment

Next, a semiconductor device 200 according to a second embodiment and amethod of manufacturing the same will be described. While thesemiconductor device 200 is different from the above-describedsemiconductor device 100 in a manufacturing method, its shape andstructure are substantially the same as those of the above-describedsemiconductor device 100, and thus, description of the shape andstructure will be omitted. In addition, the reference signs ofindividual portions will also be denoted by the same reference signs asthose of the semiconductor device 100.

FIGS. 10A-11B are diagrams schematically illustrating a method ofmanufacturing main portions of the semiconductor device 200 (thesemiconductor device 200 itself is not illustrated). Note that FIGS.10A-11B illustrate steps different from the manufacturing method of thesemiconductor device 100 alone.

Steps before forming the through hole 11A and the step of forming theelectrode within the through hole 11 in the semiconductor device 200 aresimilar to the steps in the method of manufacturing the semiconductordevice 100 (FIGS. 2A and 2B, FIGS. 3A and 3B, and FIG. 7B).

In the present embodiment, an additional insulating film 32A is adheredto be formed beforehand on the insulating film 30A (FIG. 10A) in aperiod after formation of the through hole 11A and before formation ofthe carbon-containing thin film 50 and engraving of the bottom of thethrough hole 11A. That is, the low coverage additional insulating film32A formed in a separate process from the insulating film 30A is formedso as to cover the insulating film 30A at least in the vicinity of theopening of the through hole 11A on the back surface 10 b of thesemiconductor substrate 10.

The additional insulating film 32A is formed by using at least one ofSiO₂, SiON, or SiN. The manufacturing method is similar to the methodfor forming the additional insulating film 32 described in the firstembodiment. For example, the film of SiO₂ is formed by using the PE-CVDmethod that uses SiH₄ or tetraethoxysilane (TEOS) as a precursor gas.The thickness of the additional insulating film 32A may be at a levelthat would not vanish during the etching or ashing performed at theengraving of the bottom of the through hole 11A, and at a level thatwould not damage the insulating film 30A (corresponding to theinsulating film main body 31) during the etching or ashing performed atthe engraving of the bottom of the through hole 11A.

The additional insulating film 32A is formed as a thin film with lowcoverage. Accordingly, as illustrated in FIG. 10B, the amount ofadhesion formed on the back surface 10 b of the semiconductor substrate10 is large whereas the amount of adhesion to the inner surface of thethrough hole 11A is small. Therefore, the film thickness graduallydecreases toward the deeper portion of the through hole 11A in thevicinity of the opening of the through hole 11A (in the range of severalnm to several tens nm from the opening).

Next, the bottom of the through hole 11A is engraved by etching toachieve a depth at which the bottom of the hole reaches the metal film22 (FIGS. 10B to 11B). The present embodiment also uses a technique ofetching that suppresses occurrence of damage to the insulating film 30Aother than the bottom of the through hole 11A.

First, a carbon-containing thin film 50 for protecting the additionalinsulating film 32A (particularly the additional insulating film 32A inthe vicinity of the opening of the through hole 11A) formed along theback surface 10 b of the semiconductor substrate 10 is formed (FIG.10B). It is possible to form the carbon-containing thin film 50 by usingplasma having at least one of fluorocarbons CF4, C4F8, C4F6, etc.) orhydrofluorocarbons (CHF3, CH2F2, CH3F, C5HF7, etc.) as the process gasin a low ion energy state (for example, substrate bias of 100V or less).Note that the process gas may contain at least one of hydrocarbon (CH4,C2H4, etc.), He, Ar, O2, CO, or N2.

The carbon-containing thin film 50 is formed as a thin film with lowcoverage. Therefore, as illustrated in FIG. 10B, while thecarbon-containing thin film 50 adheres to be formed on the back surface10 b side of the semiconductor substrate 10 with a constant thickness ormore, the adhesion formation of the film onto the inner surface of thethrough hole 11A is in such a degree that the film thickness graduallydecreases toward the deeper portion of the through hole 11A in thevicinity of the opening of the through hole 11A (in the range of aboutseveral nm to several tens nm from the opening). The carbon-containingthin film 50 is formed with a thickness of, for example, about 10 nm to100 nm on the back surface 10 b side of the semiconductor substrate 10.

The carbon-containing thin film 50 is formed in a shape protrudingtoward the center of the through hole 11A in the vicinity of the openingof the through hole 11A, and the film thickness gradually decreasestoward the deeper portion of the through hole 11A as described above,leading to an overhanging shape of the carbon-containing thin film 50 inthe vicinity of the opening of the through hole 11A. The protrusionamount x toward the center of the through hole 11A of thecarbon-containing thin film 50 is about 3 nm in a case where thethickness d of the carbon-containing thin film 50 is about 10 nm to 100nm. In the present embodiment, the additional insulating film 32A of lowcoverage is adhered to be formed beforehand on the insulating film 30A,and the additional insulating film 32A also has a shape protrudingtoward the center of the through hole 11A similarly to thecarbon-containing thin film 50. Accordingly, assuming that theadditional insulating film 32A has a protrusion amount of 3 nm, forexample, the through hole 11A having an opening width of about 50 nm ina state where the insulating film 30A is adhered is going to have anopening with of about 37 nm in a state where the additional insulatingfilm 32A and the carbon-containing thin film 50 are formed.

The bottom of the through hole 11A having such an opening width isengraved by anisotropic plasma etching using the carbon-containing thinfilm 50 as a mask (FIG. 11A). This anisotropic plasma etching method issimilar to the case of the first embodiment described above.

Next, the carbon-containing thin film 50 and the C polymer adheredduring the anisotropic plasma etching are removed by ashing (FIG. 11B).This ashing method is also similar to the case of the above-describedfirst embodiment.

Thereafter, similarly to the first embodiment, processing of forming thecarbon-containing thin film 50 by using plasma deposition again, plasmaetching using the carbon-containing thin film 50 as a mask, and ashingof removing the carbon-containing thin film 50 and the C polymer adheredduring etching is repeatedly performed in a short cycle so as togradually engrave the bottom of the through hole 11A until the bottom ofthe through hole 11A reaches the metal film 22 to form the through hole11.

Note that the additional insulating film 32A may be partially orentirely removed by a method such as CMP before burying the barriermetal and the metal, for example, or may be used as it is.

With the method of manufacturing the semiconductor device 200 accordingto the present embodiment described above, there is an advantage ofbeing able to suppress the damage to the high coverage insulating film30A initially formed to an extremely low level in addition to theadvantages of the manufacturing method of the semiconductor device 100according to the above-described first embodiment.

(C) Third Embodiment

Next, a semiconductor device 300 according to a third embodiment and amethod of manufacturing the same will be described. While thesemiconductor device 300 is different from the above-describedsemiconductor device 100 in a manufacturing method, its shape andstructure are substantially the same as those of the above-describedsemiconductor device 100, and thus, description of the shape andstructure will be omitted. In addition, the reference signs ofindividual portions will also be denoted by the same reference signs asthose of the semiconductor device 100.

FIGS. 12A-13B are diagrams schematically illustrating a method ofmanufacturing main portions of the semiconductor device 300 (thesemiconductor device 300 itself is not illustrated). Note that FIGS.12A-13B illustrate steps different from the manufacturing method of thesemiconductor device 100 alone.

Steps before forming the through hole 11A and the step of forming theelectrode within the through hole 11 in the semiconductor device 300 aresimilar to the steps in the method of manufacturing the semiconductordevice 100 (FIGS. 2A and 2B, FIGS. 3A and 3B, and FIG. 7B).

Furthermore, the present embodiment also performs processing, after theformation of the through hole 11A, of engraving the bottom of thethrough hole 11A by etching so as to achieve the depth at which thebottom of the through hole 11A reaches the metal film 22. The presentembodiment also uses a technique of etching that suppresses occurrenceof damage to the insulating film 30 other than the bottom of the throughhole 11A.

However, this takes a configuration in which the step of repeatedlyperforming processing of: plasma deposition of the carbon-containingthin film 50 (FIG. 12A); the plasma etching using the carbon-containingthin film 50 as a mask (FIG. 12B); and ashing of removing thecarbon-containing thin film 50 and the C polymer adhered during theetching in a short period is different from the above in that ashing isnot performed every period but performed just after the plasmadeposition and the plasma etching are repeated a plurality of times in ashort cycle. That is, the configuration is different from the firstembodiment in that ashing is not performed after the plasma depositionof the carbon-containing thin film 50 (FIG. 12A) and after the plasmaetching using the carbon-containing thin film 50 as a mask (FIG. 12B),and that plasma deposition of stacking the carbon-containing thin film50 further on the remaining carbon-containing thin film 50 (FIG. 13A),and that plasma etching using the carbon-containing thin film 50remaining in the previous step and the carbon-containing thin film 50stacked thereon as a mask (d)) is performed (FIG. 13B).

In this manner, the carbon-containing thin film 50 used as a mask whilebeing stacked is completely removed by ashing once at a stage where theclosure of the opening of the through hole 11A becomes unacceptable, andthen, the carbon-containing thin film 50 is newly deposited on theinsulating film 30A. In this manner, the bottom of the through hole 11Ais gradually engraved while adding and updating the carbon-containingthin film 50 as a mask for plasma etching, the bottom of the throughhole 11A reaches the metal film 22 to form the through hole 11. Thesteps after this processing are similar to the first embodimentdescribed above.

With the manufacturing method according to the present embodimentdescribed above, there is no need to perform ashing every time plasmaetching is performed, making it possible to improve efficiency of themanufacturing steps.

(D) Fourth Embodiment

Next, a semiconductor device 400 according to a fourth embodiment and amethod of manufacturing the same will be described. After forming thewiring layer 420 on a semiconductor substrate 410, the semiconductordevice 400 forms, as an example, a through-substrate electrode 412penetrating through the wiring layer 420 from a back surface 410 b sideof the semiconductor substrate 410 to reach a metal electrode pad 460provided near a front surface 410 a.

FIGS. 14 to 16 are diagrams schematically illustrating a method ofmanufacturing main portions of the semiconductor device 400 according tothe present embodiment.

As illustrated in FIG. 14, the method of manufacturing the semiconductordevice 400 includes: first forming a through hole 411A to penetrate thesemiconductor substrate 410; and stacking an insulating film 430A overthe entire surface including the back surface 410 b of the semiconductorsubstrate 410 and an inner surface of the through hole 411A. Thesemiconductor substrate 410, the through hole 411A, and the insulatingfilm 430A respectively correspond to the semiconductor substrate 10, thethrough hole 11A, and the insulating film 30A of the first embodiment.

Thereafter, similarly to the engraving of the bottom of the through hole11A in the first embodiment, the bottom of the through hole 411A isengraved by processing of plasma deposition, plasma etching, and ashingrepeatedly performed in a short cycle, so as to form a through hole 411that penetrates through the wiring layer 420 to reach the metalelectrode pad 460 (FIG. 15). The through hole 411 is a configurationcorresponding to the through hole 11 of the first embodiment. Note thatat engraving the wiring layer 420, etching is performed whileappropriately changing etching conditions in accordance with individualfilm types of the stacked film constituting the wiring layer 420.

For the through hole 411 thus formed, similarly to the through hole 11of the first embodiment, a through-substrate electrode 412 (TSV) isformed by burying a barrier metal film and a metal (not illustrated)into the through hole 411 (FIG. 16).

In this manner, with the manufacturing method of the semiconductordevice 400 according to the present embodiment, the through hole 411penetrating the wiring layer 420 can be formed by the processingperformed in the same plasma device, making it possible to eliminate thenecessity of using a lithography technology in the processing ofengraving the bottom of the through hole 411A to penetrate the wiringlayer 420. In addition, processing of the bottom of the through hole411A is stabilized. Furthermore, since the carbon-containing thin film50 is easy to remove, the influence on the subsequent process can beminimized.

(E) Fifth Embodiment

Next, a semiconductor device 500 according to a fifth embodiment and amethod of manufacturing the same will be described. The semiconductordevice 500 is formed by stacking lamination of a plurality of elementsincluding a wiring layer or the like on a semiconductor substrate. Thisexample includes: a through-substrate electrode penetrating at least oneelement to be connected to an electrode of another element; and athrough-substrate electrode penetrating solely the semiconductorsubstrate of the same single element to be connected to an electrode inthe wiring layer within the same element.

FIGS. 17 to 20 are diagrams schematically illustrating a method ofmanufacturing a main portion of the semiconductor device 500 accordingto the present embodiment.

As illustrated in FIGS. 17 to 20, the semiconductor device 500 is formedby adding processing to be described later to a combination obtained byjoining a first element X and a second element Y by lamination. In thefirst element X, a wiring layer 520X is formed on a semiconductorsubstrate 510X. In the second element Y, a wiring layer 520Y is formedon a semiconductor substrate 510Y. The first element X and the secondelement Y are joined with each other by lamination with the wiring layer520X side and the wiring layer 520Y side facing each other.

Hereinafter, a boundary between the first element X and the secondelement Y will be referred to as a joining surface Z.

Accordingly, in the semiconductor device 500, the wiring layer 520X islocated at a position more toward the joining surface Z than thesemiconductor substrate 510X within the first element X, while thewiring layer 520Y is located at a position more toward the joiningsurface Z than the semiconductor substrate 510Y within the secondelement Y.

As illustrated in FIG. 17, a through hole 511A and a through hole 511Bare formed (FIG. 17) as a first step of the method of manufacturing thesemiconductor device 500. The through hole 511A is formed to penetratethrough the semiconductor substrate 510X from the back surface llb andhaving a depth not reaching the metal film 522 as a connection target ofthe wiring layer 520X of the first element X. The through hole 511B isformed to go beyond the joining surface Z from the back surface 510b toreach the second element Y and having a depth not reaching a metalelectrode pad 560 formed in the wiring layer 520Y of the second elementY.

The through hole 511A and the through hole 511B are formed by a methodsimilar to the method for forming the through hole 11A of theabove-described first embodiment. For example, etching is performedafter resist formation on the opening of the forming range of thethrough hole 511A and on the back surface 510 b so as to form thethrough hole 511A, and thereafter, the resist is removed once. Next,while burying the resist in the formed through hole 511A for protection,etching is performed after resist formation on the opening of theforming range of the through hole 511B and on the back surface 510 b soas to form the through hole 511B, and thereafter, the resist is removed.With this processing, the through hole 511A and the through hole 511Bare formed.

Next, an insulating film 530A with high coverage is formed over theentire surface of the back surface 510 b of the semiconductor substrate510X, the entire inner side surface of the through hole 511A, and theentire inner surface of the through hole 511B (FIG. 18). The insulatingfilm 530A is formed using the similar material and manufacturing methodas the insulating film 30A of the first embodiment.

Thereafter, the inner bottom surfaces of the through hole 511A and thethrough hole 511B are engraved by the method similar to the method ofengraving the inner bottom surface of the through hole 11A of the firstembodiment (FIG. 19). In the present embodiment, the through hole 511Bis engraved toward the metal film 522 constituting the wiring layer 520Xof the first element X, while the through hole 511A is engraved towardthe metal electrode pad 560 constituting the wiring layer 520Y of thesecond element Y. Note that it is desirable that the engraving of theinner bottom surface of the through hole 511A and the engraving of theinner bottom surface of the through hole 511B be completed almost at thesame time. For example, at formation of the through hole 511A and thethrough hole 511B, the depths of the through hole 511A and the throughhole 511B are formed so that the distance between the inner bottomsurface of the through hole 511B and the metal film 522 is substantiallyequal to the distance between the inner bottom surface of the throughhole 511A and the metal electrode pad 560.

Subsequently, similarly to the through hole 11 of the first embodiment,a barrier metal film (not illustrated) and a metal are buried in thethrough hole 511A and the through hole 511B respectively penetrating themetal electrode pad 560 and the metal film 522 so as to formthrough-substrate electrodes 512A and 512B (FIG. 20). Thethrough-substrate electrode 512A and the through-substrate electrode512B are electrically connected to each other by a metal film 570 formedalong the back surface 510b of the semiconductor substrate 510X.

As described above, with the manufacturing method of the semiconductordevice 500 according to the present embodiment, it is possible to formthe through hole 511A and the through hole 511B penetrating the wiringlayer 520 in parallel in processing performed in the same plasmaapparatus without using a lithography technology. In addition,processing of the bottoms of the through hole 511A and the through hole511B is stabilized. Furthermore, since the carbon-containing thin film50 is easy to remove, the influence on the subsequent process can beminimized.

(F) Sixth Embodiment

Next, a semiconductor device 600 according to a sixth embodiment and amethod of manufacturing the same will be described. The semiconductordevice 600 is formed by stacking lamination of a plurality of elementsincluding a wiring layer or the like on a semiconductor substrate, andis an example in which a through-substrate electrode penetrating throughat least one element to be connected to an electrode of another elementis connected to another electrode in the middle via side contact.

FIGS. 21 to 23 are diagrams schematically illustrating a method ofmanufacturing a main portion of the semiconductor device 600 accordingto the present embodiment.

As illustrated in FIGS. 21 to 23, similarly to the semiconductor device500 according to the fifth embodiment, the semiconductor device 600 isformed by adding processing to be described later to a combinationobtained by joining the first element X and the second element Y bylamination.

First, a through hole 611A is formed in the semiconductor device 600(FIG. 21). The through hole 611A is formed to penetrate through asemiconductor substrate 610X and having a depth not reaching a metalfilm 622 as a connection target of a wiring layer 620X of the firstelement X. Note that the through hole 611A and the metal film 622overlap each other in plan view from the back surface 610 b side of thesemiconductor substrate 610X, indicating that there is a positionalrelationship such that the end portion of the through hole 611Apartially overlaps the end portion of the metal film 622.

Next, an insulating film 630A with high coverage is stacked over theentire surface including the back surface 610 b of the semiconductorsubstrate 610X and the inner surface of the through hole 611A (FIG. 22).The insulating film 630A is formed by the material and manufacturingmethod similar to those of the insulating film 30A of the firstembodiment.

Thereafter, the first engraving is performed on the inner bottom surfaceof the through hole 611A (FIG. 23) by the method substantially similarto the method of engraving the inner bottom surface of the through hole11A of the first embodiment. In the present embodiment, the through hole611A is engraved toward the metal electrode pad 660 constituting awiring layer 620Y of the second element Y.

However, a first engraving hole 611A1 formed in first engraving isformed by simply engraving a portion of the inner bottom surface of thethrough hole 611A. Specifically, the first engraving hole 611A1 isformed by engraving a range not interfering with the metal film 622 in aplan view from the back surface 610 b side of the semiconductorsubstrate 610X. Therefore, the first engraving hole 611A1 reaches themetal electrode pad 660 with no exposure of the metal film 622 in themiddle.

After completion of the formation of the first engraving hole 611A1 inthis manner, second engraving of engraving another inner bottom surfaceof the through hole 611A is performed to form a second engraving hole611A2 having a depth to reach the metal film 622 (FIG. 24). The secondengraving can also be defined as engraving to expand the first engravinghole 611A1 to a depth to reach the metal film 622. This process exposesthe metal film 622 in the middle of the second engraving hole 611A2 (theside surface of the lower end portion and the corner portion of thebottom surface).

For the through hole 611 thus formed, similarly to the through hole 11of the first embodiment, a through-substrate electrode 612 is formed byburying a barrier metal film and a metal (not illustrated) inside theinsulating film 630 formed in the through hole 611 (FIG. 25). Thethrough-substrate electrode 612 is connected to the metal electrode pad660 at the inner end thereof and comes in side contact with the metalfilm 622 on the way. This makes it possible to form the through hole 611that penetrates through the wiring layer 620X and in which both themetal electrode pad 660 and the metal film 622 are exposed in the holeby the processing performed in the same plasma apparatus without using alithography technology. In addition, processing of the bottom of thethrough hole 611A is stabilized. Furthermore, since thecarbon-containing thin film 50 is easy to remove, the influence on thesubsequent process can be minimized.

Here, a difference between the first engraving and the second engravingwill be described with reference to FIGS. 26A-28B. Diagrams illustratedin FIGS. 26A-28B correspond to the engraving method in which processingincluding: plasma deposition of the carbon-containing thin film 50; theplasma etching using the carbon-containing thin film 50 as a mask; andashing of removing the carbon-containing thin film 50 and the C polymeradhered during etching is repeated in a short cycle, and these diagramssimply illustrate the main points of the manufacturing method of thepresent embodiment, similar to the first embodiment.

First, at the time of forming the first engraving hole 611A1, the lowcoverage carbon-containing thin film 50 is formed to be thick so as toset the protrusion amount x which protrudes toward the center of thethrough hole 611A near the opening of the through hole 611A to a largeamount (FIG. 26A). With this setting, the opening size of the throughhole 611A is narrowed to a size substantially equal to the hole width ofthe first engraving hole 611A1.

When anisotropic plasma etching using the carbon-containing thin film 50as a mask is performed in this state, the inner bottom surface of thethrough hole 611A is etched to be substantially the same size as theopening of the narrowed through hole 611A (FIG. 26B). Thereafter,processing of plasma deposition, plasma etching, and ashing isrepeatedly performed in a short cycle so as to form the first engravinghole 611A1 (FIG. 27A) to a depth to reach the metal electrode pad 660(not illustrated in FIGS. 26A-28B).

Next, at the time of forming the second engraving hole 611A2, the lowcoverage carbon-containing thin film 50 is formed to be thin so as toset the protrusion amount x which protrudes toward the center of thethrough hole 611A near the opening of the through hole 611A to a smallamount (FIG. 27B). With this setting, the opening size of the throughhole 611A is maintained to a size substantially equal to the innerbottom surface of the through hole 611A.

When anisotropic plasma etching using the carbon-containing thin film 50as a mask is performed in this state, a range of substantially the samesize as the opening of the through hole 611A, that is, a substantiallyentire range of the inner bottom surface of the through hole 611A isetched (FIG. 28A). Thereafter, processing of the plasma deposition,plasma etching, and ashing is repeated in a short cycle, so as to formthe second engraving hole 611A2 to a depth to reach the metal film 622(FIG. 28B).

In this manner, by adjusting the thickness of the carbon-containing thinfilm 50 and adjusting the protrusion amount x protruding toward thecenter of the through hole 611A near the opening of the through hole611A, it is possible to adjust the width of the engraving hole to beformed on the inner bottom surface of the through hole 611A. Therefore,in a case where there is an object to be avoided in a layer beingengraved, the carbon-containing thin film 50 can be formed to be thickso that the engraving hole is narrowed to form a small-width engravinghole, making it easy to form the engraving hole while avoiding thethrough-substrate electrode and the object in the through hole 611.Furthermore, the metal film 622 to be connected to the through-substrateelectrode formed in the middle of the engraving hole can be managed asfollows. That is, while controlling to narrow the hole width so as notto interfere with the metal film 622 during engraving toward the metalelectrode pad 660 at a deep position, and after completion of engravinginto the metal electrode pad 660, the second engraving is performed bycontrolling the hole width to be wider so as to expose the metal film622 at a shallow position again. This method can improve processingstability of the first engraving.

Note that the present technology is not limited to each of theabove-described embodiments and modifications and includesconfigurations including mutual replacement or various modifications ofcombinations of individual formations disclosed in the above embodimentsand modifications, configurations including mutual replacement orvarious modifications of combinations of individual formations disclosedin known technologies and the above embodiments and modifications, orthe like. Furthermore, the technical scope of the present technology isnot limited to the above-described embodiments, but extends to mattersdescribed in the claims and their equivalents.

Moreover, the present technology may also be configured as below.

(1)

A semiconductor device manufacturing method including:

a first step of forming a through hole in a semiconductor substrate byusing anisotropic etching performed from a first surface side of thesemiconductor substrate;

a second step of forming a thin film being an insulating film on anentire inner surface of the through hole;

a third step of forming a carbon-containing thin film using plasmadeposition on the first surface including an opening edge portion of thethrough hole;

a fourth step of engraving an inner bottom of the through hole by usinganisotropic plasma etching with the carbon-containing thin film as amask;

a fifth step of removing the carbon-containing thin film by ashing; and

a sixth step of forming a through-substrate electrode in the throughhole.

(2)

The semiconductor device manufacturing method according to (1),

in which the carbon-containing thin film is formed by plasma depositionusing at least one of hydrocarbon, fluorocarbon, or hydrofluorocarbon,as a process gas.

(3)

The semiconductor device manufacturing method according to (1) or (2),

in which the anisotropic plasma etching in the fourth step is performedby plasma etching using at least one of a fluorocarbon or ahydrofluorocarbon, as a process gas.

(4)

The semiconductor device manufacturing method according to any one of(1) to (3),

in which the carbon-containing thin film is formed in a shape such thatthe vicinity of an opening of the through hole protrudes toward a centerof the through hole.

(5)

The semiconductor device manufacturing method according to any one of(1) to (4),

in which an additional insulating film covering at least a portion ofthe thin film being an insulating film formed in the vicinity of theopening of the through hole is formed before the sixth step.

(6)

A semiconductor device including:

a semiconductor substrate;

a wiring layer formed to be stacked on a first surface of thesemiconductor substrate;

a metal film constituting a portion of the wiring layer;

a first insulating film constituting a portion of the wiring layer andprovided adjacent to the semiconductor substrate side of the metal film;

a through-substrate electrode penetrating from the first surface of thesemiconductor substrate and from a second surface of the semiconductorsubstrate opposite to the first surface, to the metal film;

a second insulating film interposed between the through-substrateelectrode and the semiconductor substrate; and a third insulating filmformed to adhere to a second surface-side end portion of the secondinsulating film.

REFERENCE SIGNS LIST

10 Semiconductor substrate10 a Front surface10 b Back surface11 Through hole11A Through hole12 Through-substrate electrode20 Wiring layer21 Insulating film22 Metal film30 Insulating film30A Insulating film31 Insulating film main body32 Additional insulating film32A Additional insulating film

40 Resist 41 Opening

50 Carbon-containing thin film100 Semiconductor device200 Semiconductor device300 Semiconductor device400 Semiconductor device410 Semiconductor substrate410 a Front surface410 b Back surface411 Through hole411A Through hole412 Through-substrate electrode420 Wiring layer430 Insulating film430A Insulating film460 Metal electrode pad500 Semiconductor device510X Semiconductor substrate510Y Semiconductor substrate510 b Back surface511A Through hole511B Through hole512 Through-substrate electrode520 Wiring layer520X Wiring layer520Y Wiring layer522 Metal film530 Insulating film530A Insulating film560 Metal electrode pad600 Semiconductor device610X Semiconductor substrate610 b Back surface611 Through hole611A Through hole611A1 First engraving hole611A2 Second engraving hole612 Through-substrate electrode620X Wiring layer620Y Wiring layer622 Metal film630 Insulating film630A Insulating film660 Metal electrode padX First elementY Second elementZ Joining surface

1-5. (canceled)
 6. A semiconductor device comprising: a semiconductorsubstrate; a wiring layer stacked on a first surface of thesemiconductor substrate, wherein a first portion of the wiring layercomprises a metal film and a second portion of the wiring layercomprises a first insulating film, wherein the first insulating film isprovided adjacent to a semiconductor substrate-side of the metal film; athrough-substrate electrode penetrating from a second surface of thesemiconductor substrate; a second insulating film interposed between thethrough-substrate electrode and the semiconductor substrate; and a thirdinsulating film adhered to an end portion of the second insulating filmadjacent to the second surface of the semiconductor substrate.
 7. Thesemiconductor device of claim 6, wherein the first insulating film isetched.
 8. The semiconductor device of claim 7, wherein thethrough-substrate electrode is formed to a depth reaching a midway depthof the first insulating film.
 9. The semiconductor device of claim 6,wherein the second insulating film covers an inner surface of a throughhole.
 10. The semiconductor device of claim 6, wherein the secondinsulating film comprises a low dielectric constant interlayerinsulating film material.
 11. The semiconductor device of claim 6,wherein the third insulating film comprises one of SiO2, SiN, and SiON.12. The semiconductor device of claim 6, wherein the third insulatingfilm comprises a thickness between 10 nm and 100 nm.
 13. A method ofmanufacturing a semiconductor device, the method comprising: forming asemiconductor substrate; forming a wiring layer on a first surface ofthe semiconductor substrate, wherein a first portion of the wiring layercomprises a metal film and a second portion of the wiring layercomprises a first insulating film, wherein the first insulating film isprovided adjacent to a semiconductor substrate-side of the metal film;forming a through-substrate electrode penetrating from a second surfaceof the semiconductor substrate to the metal film; forming a secondinsulating film interposed between the through-substrate electrode andthe semiconductor substrate; and forming a third insulating film adheredto an end portion of the second insulating film adjacent to the secondsurface of the semiconductor substrate.
 14. The method of claim 13,wherein the first insulating film is etched.
 15. The method of claim 14,wherein the through-substrate electrode is formed to a depth reaching amidway depth of the first insulating film.
 16. The method of claim 6,wherein the second insulating film covers an inner surface of a throughhole.
 17. The method of claim 13, wherein the second insulating filmcomprises a low dielectric constant interlayer insulating film material.18. The method of claim 13, wherein the third insulating film comprisesone of SiO2, SiN, and SiON.
 19. The method of claim 13, wherein thethird insulating film comprises a thickness between 10 nm and 100 nm.20. An electronic device comprising: a semiconductor device comprising:a semiconductor substrate; a wiring layer stacked on a first surface ofthe semiconductor substrate, wherein a first portion of the wiring layercomprises a metal film and a second portion of the wiring layercomprises a first insulating film, wherein the first insulating film isprovided adjacent to a semiconductor substrate-side of the metal film; athrough-substrate electrode penetrating from a second surface of thesemiconductor substrate to the metal film; a second insulating filminterposed between the through-substrate electrode and the semiconductorsubstrate; and a third insulating film adhered to an end portion of thesecond insulating film adjacent to the second surface of thesemiconductor substrate.
 21. The electronic device of claim 20, whereinthe first insulating film is etched.
 22. The electronic device of claim21, wherein the through-substrate electrode is formed to a depthreaching a midway depth of the first insulating film.
 23. The electronicdevice of claim 20, wherein the second insulating film covers an innersurface of a through hole.
 24. The electronic device of claim 20,wherein the second insulating film comprises a low dielectric constantinterlayer insulating film material.
 25. The electronic device of claim20, wherein the third insulating film comprises one of SiO2, SiN, andSiON.